IBM publication "Technical Disclosure Bulletin," Vol. 26, No. 3A, August 1983, pages 990-991, I. Hernandez, Jr.: "Frequency multiplier using delay circuits" describes a frequency multiplier formed by a chain of delay circuits whose outputs are connected to the respective inputs of a tree of XOR gates. The tree illustrated in this publication is made of gates which have two inputs and one output connected to an input of a gate in the next layer, and in which the other input is directly connected to the output of a respective delay circuit in the chain. Each gate thus constitutes a different layer of the tree. In other words, the tree has as many layers as the chain has delay circuits, and each layer has two branches, one of which returns to the preceding gates, and the other of which accesses a respective output of the chain. There is, therefore, an asymmetry in the time required for the propagation of signals in the two branches. This asymmetry increases proportionally as the output of the tree is approached. Therefore, in the output signal of the tree, the pulse repetition period of the same edge can vary greatly if frequency is increased. The frequency multiplier described in this publication is therefore not adapted for very high frequencies, for example greater than one gigabit per second.
European patent disclosure EP-A-0441684 describes a frequency multiplier in which the successive outputs of the chain of delay circuits are driven by a phase locked loop and are all applied to the respective inputs of the first layer of the tree of XOR gates. The subsequent layers have an integrated circuit arrangement of a, whereas the last layer has only one gate. This tree, then, assures a propagation which is roughly the same for each of the input signals and is suitable for very high frequencies.
However, at such high frequencies, the tree must guarantee equal propagation times from its respective inputs to the output, regardless of the edge to be propagated. When this is the case, the tree is said to be symmetrical. Symmetry implies that all the gates of the tree are arranged identically in the integrated circuit, that they produce equal propagation times regardless of the active input and the edge to be propagated, and that their loads are identical.
In attempting to satisfy all these requirements, a first problem arises due to the fact that an XOR-type gate may or may not be able to invert a signal that is applied to its first input, depending on the state of the second input, a state which remains stable during switching. Consequently, depending on the states of the inputs of the tree, a leading edge at the output can only be generated by leading edges in the tree, by a majority of trailing edges or by any intermediate configuration. The converse also applies to a trailing edge at the output of the tree.
Other problems arise in employing the technology of integrated circuits using complementary field effect transistors with insulated gates, which is currently called CMOS (Complementary Metal Oxide Silicon) technology. This technology offers the advantage of using gates based on an inventor circuit which simply includes two complementary NMOS (N type) and PMOS (p type) transistors connected in series between the two supply potentials Vdd and Vss. The input signal is applied to the gates of the two transistors and the output signal is supplied at the linkage point of the drains of the two transistors. The PMOS transistor assures the output switching of the leading edges, while the trailing edges are generated by the NMOS transistor. This asymmetry, which is inherent to this technology, makes it impossible to satisfy of the requirement for the symmetry of the tree. This requirement has particular repercussions for the equalization of the loads. This last requirement is partially satisfied by equalizing the wiring lengths between adjacent gates, but the problem essentially lies in the equalization of the internal loads of such gates.
Finally, assuming that these two problems have been resolved, it is still necessary for the direct and inverted inputs of the input gates of the tree to permutate simultaneously in opposite directions. This condition does not generally arise in CMOS technology, in which the only way to obtain the inverse of a signal is to add an inverter. However, due to the transit time of this inverter, the direct signal and its inverse do not switch at exactly the same moment.
On the other hand, bipolar transistor technologies make it possible to obtain better dynamic performances, especially higher throughputs. Bipolar transistors naturally lend themselves to symmetrical arrangements, particularly due to the utilization of differential ECL (Emitter-Coupled Logic) or CML (Common Mode Logic) layouts. However, the higher throughputs increase the requirements for the symmetry of the tree and necessitate specific layouts. In ECL logic, a standard XOR gate is made from two superposed differential stages which are connected in series (series gating) and which, respectively, receive the complementary signals of the two inputs. This layout has the disadvantage of having different propagation times for the two inputs, since the complementary signals which issue from the lower stage must transit the upper stage. Thus, in addition to the first problem mentioned above relative to the various states of the inputs of the tree, these gates pose the same problem as the transistors in series in the CMOS branches.